| Bachelor Thesis: High-Level Synthesis (HLS) Optimization for Machine Learning Algorithms |
Mahboobe Sadeghipourrudsari |
| Bachelor Thesis: Integrating a Camera into a RISC-V SoC on an FPGA |
Dr.-Ing. Jonas Krautter |
| Bachelor/Master Thesis: "SpikeSynth: A Robust Analog Printed Spiking Neuromorphic Circuit with Learnable Spike Generator" |
Priyanjana Pal / Tara Gheshlaghi
|
| Bachelor/Master Thesis: Accelerating Neural Networks in FPGAs |
M.Sc. Vincent Meyers / Dr.-Ing. Dennis Gnad |
| Bachelor/Master Thesis: Security of Neural Network Hardware Accelerators |
Dr.-Ing. Dennis Gnad |
| Bachelor/Master Thesis: Side-Channel Countermeasures in FPGAs |
M.Sc. Sergej Meschkov / Dr.-Ing. Dennis Gnad |
| Master Thesis: Accelerating Automotive Workloads through RISC-V Extensions and Hardware Accelerators |
Dr.-Ing. Jonas Krautter |
| Master Thesis: Developing and Evaluating Stochastic Binarized/Quantized Activations for Uncertainty Estimation in Binary Neural Networks |
M.Sc. Soyed Tuhin Ahmed |
| Master/Bachelor Thesis: Side channel attack on HDC Accelerators |
Mahboobe Sadeghipourrudsari / Vincent Meyers |
| Master/Bachelor Thesis: position on Bayesian Deep Learning |
M.Sc. Soyed Tuhin Ahmed |
| Master/Bachelor Thesis: position on Reliable Deep Learning |
M.Sc. Soyed Tuhin Ahmed |
