Short Bio

Surendra Hemaram received his B.E. (Bachelor of Engineering) in Instrumentation Engineering from University of Mumbai, Mumbai, India and his M.Tech. (Master of Technology) in Electrical Engineering from Indian Institute of Technology (IIT) Jodhpur, Rajasthan, India in 2016 and 2021 respectively. In his master thesis, he worked on application of Metaheuristic Optimization techniques for designing circuits & systems, Power Delivery Network (PDN) Optimization and variability analysis of circuits and systems. In November 2021 he joined the CDNC group of Prof. Mehdi B.Tahoori at KIT University, Karlsruhe, Germany. His current research interest includes VLSI design, Spintronics Based Computing, and non-volatile memories.

Publications

Conferences
Soyed Tuhin Ahmed, Surendra Hemaram, Mehdi B. Tahoori Embedding Neural Network Parameters with Self Error Correcting Coding using Multi-task Learning in 42nd VLSI Test Symposium (VTS), 2024.

Former Publications
Surendra Hemaram and Jai Narayan Tripathi Surendra Hemaram and Jai Narayan Tripathi IEEE Electromagnetic Compatibility Magazine, 2021
Aksh Chordia, Surendra Hemaram and Jai Narayan Tripathi Aksh Chordia, Surendra Hemaram and Jai Narayan Tripathi IEEE Workshop on Signal and Power Integrity (SPI), 2021
Aksh Chordia, Surendra Hemaram and Jai Narayan Tripathi A Swarm Intelligence based Automated Framework for Variability Analysis IEEE Latin America Microwave Conference (LAMC), 2021.
Surendra Hemaram, Jai Narayan Tripathi Metaheuristic Optimization of Decoupling Capacitors in a Power Delivery Network Joint IEEE International Symposium on Electromagnetic Compatibility, Signal and Power Integrity and EMC Europe (EMC+SIPI), 2021.
Surendra Hemaram, Jai Narayan Tripathi Optimal Design of a Decoupling Network Using Variants of Particle Swarm Optimization Algorithm 2021 IEEE International Symposium on Circuits and System (ISCAS), 2021