M.Tech. Surendra Hemaram
- PhD Student
- room: A3.19
- phone: +49 721 608 47586
- fax: +49 721 608 43962
- surendra hemaram ∂does-not-exist.kit edu
Short Bio
Surendra Hemaram received his B.E. (Bachelor of Engineering) in Instrumentation Engineering from University of Mumbai, Mumbai, India and his M.Tech. (Master of Technology) in Electrical Engineering from Indian Institute of Technology (IIT) Jodhpur, Rajasthan, India in 2016 and 2021 respectively. In his master thesis, he worked on application of Metaheuristic Optimization techniques for designing circuits & systems, Power Delivery Network (PDN) Optimization and variability analysis of circuits and systems. In November 2021 he joined the CDNC group of Prof. Mehdi B.Tahoori at KIT University, Karlsruhe, Germany. His current research interest includes VLSI design, Spintronics Based Computing, and non-volatile memories.
Publications
| Journals | |
|---|---|
| Surendra Hemaram; Mehdi B. Tahoori; Francky Catthoor; Siddharth Rao; Sebastien Couet; Tommaso Marinelli Asymmetric and Adaptive Error Correction in STT-MRAM IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (Volume 44, Issue 9), DOI, PDF, Feb 2025. | |
| Surendra Hemaram, Mehdi B. Tahoori, Francky Catthoor, Siddharth Rao, Sebastien Couet, Valerio Pica, Gouri Sankar Kar Soft and Hard Error-Correction Techniques in STT-MRAM in IEEE Design & Test (Volume 41, Issue 5), DOI, PDF, Oct 2024. |
| Conferences | |
|---|---|
| Surendra Hemaram, Mahta Mayahinia, Mehdi B. Tahoori, Francky Catthoor, Siddharth Rao, Sebastien Couet, Tommaso Marinelli, Anita Farokhnejad, Gouri Sankar Kar InterA-ECC: Interconnect-Aware Error Correction in STT-MRAM Design, Automation & Test in Europe Conference (DATE), DOI, PDF, Mar 2025. | |
| Soyed Tuhin Ahmed; Surendra Hemaram; Mehdi B. Tahoori NN-ECC: Embedding Error Correction Codes in Neural Network Weight Memories using Multi-task Learning in IEEE 42nd VLSI Test Symposium (VTS), DOI, PDF, Apr 2024. | |
| Surendra Hemaram; Mehdi B Tahoori; Francky Catthoor; Siddharth Rao; Sebastien Couet; Gouri Sankar Kar Hard Error Correction in STT-MRAM in 29th Asia and South Pacific Design Automation Conference (ASP-DAC), DOI, PDF, Jan 2024. | |
| Surendra Hemaram; Mahta Mayahinia; Mehdi B. Tahoori Adaptive Block Error Correction for Memristive Crossbars in IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS), DOI, PDF, Sep 2022. | |
| M. Sadeghipourrudsari, S. Hemaram, M. Tahoori Non-Uniform Error Correction for Hyperdimensional Computing Edge Accelerators in IEEE European Test Symposium (ETS), 2025. | |
| Soyed Tuhin Ahmed*, Surendra Hemaram*, Mehdi B. Tahoori Embedding Neural Network Parameters with Self Error Correcting Coding using Multi-task Learning in 42nd VLSI Test Symposium (VTS), 2024. |
| Former Publications |
|---|
| Surendra Hemaram and Jai Narayan Tripathi Surendra Hemaram and Jai Narayan Tripathi IEEE Electromagnetic Compatibility Magazine, 2021 |
| Aksh Chordia, Surendra Hemaram and Jai Narayan Tripathi Aksh Chordia, Surendra Hemaram and Jai Narayan Tripathi IEEE Workshop on Signal and Power Integrity (SPI), 2021 |
| Aksh Chordia, Surendra Hemaram and Jai Narayan Tripathi A Swarm Intelligence based Automated Framework for Variability Analysis IEEE Latin America Microwave Conference (LAMC), 2021. |
| Surendra Hemaram, Jai Narayan Tripathi Metaheuristic Optimization of Decoupling Capacitors in a Power Delivery Network Joint IEEE International Symposium on Electromagnetic Compatibility, Signal and Power Integrity and EMC Europe (EMC+SIPI), 2021. |
| Surendra Hemaram, Jai Narayan Tripathi Optimal Design of a Decoupling Network Using Variants of Particle Swarm Optimization Algorithm 2021 IEEE International Symposium on Circuits and System (ISCAS), 2021 |