Description:

In this thesis, students will implement and optimize machine learning algorithms on hardware using using High-Level Synthesis (HLS). HLS converts high-level code (e.g. C, C++) into a hardware description language (HDL) and thus enables the development of customized hardware accelerators for Field Programmable Gate Arrays (FPGAs). The target model for machine learning in this thesis is Hyperdimensional Computing (HDC), an emerging approach to machine learning that is particularly suited for classification tasks on low-power, hardware-constrained devices such as IoT edge devices where processing must be done locally. Students will evaluate their designs in terms of performance, power consumption, and area efficiency. They will also explore the trade-offs between hardware and software implementations of these algorithms and how HLS can accelerate computation in resource-constrained environments.

Minimum Requirements:

Programming Skills: Experience in C/C++ (to do HLS) and Python, and PyTorch (to train the model) is essential.
Basic Knowledge of Machine Learning: Familiarity with machine learning algorithms or a great passion to learn it.
Understanding of Digital Design: A basic knowledge of digital circuits, hardware description languages (HDL), and computer architecture will be beneficial.
Experience with HLS Tools (Preferred but not required): Any previous experience with tools like Xilinx Vivado HLS, Intel HLS, or similar frameworks is an advantage.
Problem-solving Skills: Ability to analyze and optimize complex algorithms and hardware designs.

Contact:

Mahboobe Sadeghipourrudsari