Description:

Computer vision and the associated decision making has become one of the most important applications for high performance edge computing, for instance, in autonomous vehicles.
To improve existing edge computers for these emerging applications, softcores programmed on Field Programmable Gate Arrays (FPGAs) are an ideal experimentation platform, as their hardware can be adapted flexibly.
The open Instruction Set Architecture (ISA) RISC-V, allows to investigate performance improvements that can be achieved through additional instructions for operations, that are typical in computer vision workloads.
Therefore, being able to use actual camera equipment with an existing RISC-V implementation is an important component in ongoing research on autonomous edge computing.

In this bachelor thesis, which is supervised jointly by the Chair of Dependable Nano-Computing (Prof. Tahoori) and Intel Labs, you will integrate a camera into an existing RISC-V implementation.
The experimental platform will be based around the LiteX framework (https://github.com/enjoy-digital/litex), which you will use to deploy a RISC-V SoC in hardware onto an FPGA.
You will learn about RISC-V and FPGAs on the hardware side as well as Linux kernel development to make the equipment accessible by user space software.
Eventually, you will be able to evaluate known workloads inside the completed system, to provide a baseline for future performance improvements.

Requirements:

    • Basic knowledge of algorithms and data structures
    • Knowledge of C/C++ programming and Linux
    • Basic knowledge of digital circuits
    • Ideally: FPGA/computer vision/kernel development experience

Keywords:

FPGAs, RISC-V, Linux, Automotive, Hardware, Accelerator

Contact:

Jonas Krautter, jonas.krautter@kit.edu, 0721/608-47684
Fabian Oboril, fabian.oboril@intel.com