Short Bio

Mahboobe Sadeghipourrudsari received her bachelor's degree in 2016 as a top-ranked student in computer engineering from Guilan University, Iran. In 2020, she graduated with a Masters in computer engineering from the University of Tehran, Iran. In her master's thesis, she worked on the development of a long-short term memory (LSTM) neural network accelerator. In 2023, she enrolled as a PhD student in the ITEC/CDNC group under the supervision of Prof. Mehdi Tahoori. Her current research interests include hardware design, functional safety, and security of edge devices, with a focus on FPGA-based accelerators.

Publications

Conferences
M. Sadeghipourrudsari, J. Krautter, M. Tahoori OTFGEncoder-HDC: Hardware-efficient Encoding Techniques for HyperdimensionalComputing in Proceedings of Design, Automation & Test in Europe (DATE), Spain, Mar 2024.
M. Sadeghipourrudsari, J. Krautter, V. Meyers, M. Tahoori E3HDC: Energy Efficient Encoding for Hyper-Dimensional Computing on Edge Devices in 34th International Conference on Field-Programmable Logic and Applications (FPL), 2024.
V. Meyers, M. Hefenbrock, M. Sadeghipourrudsari, D. Gnad, M. Tahoori Towards Functional Safety of Neural Network Hardware Accelerators: Concurrent Out-of-Distribution Detection in Hardware Using Power Side-Channel Analysis in Proceedings of the 30th Asia and South Pacific Design Automation Conference (ASPDAC), 2025.
M. Sadeghipourrudsari, V. Meyers, M. Tahoori CED-HDC: Lightweight Concurrent Error Detection for Reliable Hyperdimensional Computing in IEEE 43rd VLSI Test Symposium (VTS), 2025.
M. Sadeghipourrudsari, S. Hemaram, M. Tahoori Non-Uniform Error Correction for Hyperdimensional Computing Edge Accelerators in IEEE European Test Symposium (ETS), 2025.

Former Publications

Former Publications
M. Sadeghipourrudsari, A. Saber, Z. Navabi Diba: n-dimensional bitslice architecture for LSTM implementation International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2020.
M. Sadeghipourrudsari, H. T. Asl, Z. Navabi n-DiCE-LSTM: An n-Dimensional Configurable and Efficient Architecture for LSTM Accelerator Computer Society Annual Symposium on VLSI (ISVLSI), 2021.
M. Sadeghipourrudsari, P. Prinetto, E. Nouri, F. Sheikhshoaei, Z. Navabi A Secure Canary-Based Hardware Approach Against ROP ITASEC, Italy, 2022.
M. Sadeghipourrudsari, F. Sheikhshoaei, N. Maunero, P. Prinetto, Z. Navabi LiFi-CFI: Light-weight Fine-grained Hardware CFI Protection for RISC-V International Conference on Design, Test and Technology of Integrated Systems (DTTIS), 2023.
Rajabalipanah, M., M. Sadeghipourrudsari, Jahanpeima, Z., Roascio, G., Prinetto, P., & Z. Navabi Aftab: a risc-v implementation with configurable gateways for security IEEE East-West Design & Test Symposium (EWDTS), 2021.
Nosrati, N., Ghasemi, S. M. Sadeghipourrudsari, Z. Navabi Concurrent Error Detection for LSTM Accelerators European Test Symposium (ETS), 2022.