In this lab, the students become familiar with robust design strategies for FPGA platform as well as reliability evaluation using FPGAs. The lab starts with a short discussion on FPGA reliability threats (more specifically "soft errors") and some general strategies to protect the system against them. In the first phase, students implement an evaluation technique to estimate the design vulnerability. Then using this technique, the effectiveness of different protection strategies are evaluated. All experiments will be designed using the DE2-115 board with respect to an embedded processor. This lab provides a unique opportunity for students to experience the implementation of a large design on the FPGA, enhance its reliability and quantify the reliability improvements.