Mehdi Tahoori is a full professor and Chair of Dependable Nano-Computing (CDNC) at the Institute of Computer Science & Engineering (ITEC), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany. He received his PhD and M.S. degrees in Electrical Engineering from Stanford University in 2003 and 2002, respectively, and a B.S. in Computer Engineering from Sharif University of Technology in Iran, in 2000. In 2003, he joined the Electrical and Computer Engineering Department at the Northeastern University as an assistant professor where he promoted to the rank of associate professor with tenure in 2009. From August to December 2015, he was a visiting professor at VLSI Design and Education Center (VDEC), University of Tokyo, Japan. From 2002 to 2003, he was a Research Scientist with Fujitsu Laboratories of America, Sunnyvale, CA, in the area of advanced computer-aided research, engaged in reliability issues in deep-submicrometer mixed-signal very large-scale integration (VLSI) designs.
He holds several pending and granted U.S. and international patents. He has authored over 250 publications in major journals and conference proceedings on a wide range of topics, from dependable computing and emerging nanotechnologies to system biology. His current research interests include nanocomputing, reliable computing, VLSI testing, reconfigurable computing, emerging nanotechnologies, and systems biology.
Prof. Tahoori was a recipient of the National Science Foundation Early Faculty Development (CAREER) Award. He was a Program Committee member as well as a workshop, panel, and special session organizer of various conferences and symposia in the areas of VLSI testing, reliability, and emerging nanotechnologies, such as ITC, VTS, DAC, ICCAD, DATE, ETS, ICCD, ASP-DAC, GLSVLSI, and VLSI Design. He was an associate editor of ACM Journal of Emerging Technologies for Computing. He is currently an associate editor for IEEE Design and Test Magazine, coordinating editor for Springer Journal of Electronic Testing (JETTA), and associate editor of IET Computers and Digital Techniques. He received a number of best paper nominations and awards at various conferences. He is the Chair of the ACM SIGDA Technical Committee on Test and Reliability.
Ph.D. in Electrical Engineering, Stanford University, Stanford, CA, USA
Advisor: Prof. Edward J. McCluskey, Co-Advisor: Prof. Giovanni DeMicheli
Thesis topic: "Testing FPGAs"
|April 2002||M.S. in Electrical Engineering, Stanford University, Stanford, CA, USA|
B.S. Double Major in Computer Engineering and Computer Science, Sharif University of Technology (with Honors), Teheran, Iran.
Thesis topic: "Testability Considerations during High-Level Synthesis"
|2009-now||Chaired Full Professor, Faculty of Informatik, Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany|
|2008-2009||Associate Professor, Electrical and Computer Engineering, Northeastern University, Boston, MA, USA|
|2003-2008||Assistant Professor, Electrical and Computer Engineering, Northeastern University, Boston, MA, USA|
Research Scientist, Fujitsu Labs of America (FLA), Sunnyvale, CA, USA
CAD Consultant, Tavanza Inc., Sunnyvale, CA, USA
Summer Intern, Xilinx Inc., San Jose, CA, USA
Senior CAD Engineer, EMAD Semicon Corp., Teheran, Iran