Chair of Dependable Nano Computing (CDNC)

Testing Digital Systems I

  • type: Vorlesung (V)
  • semester: SS 2019
  • time: 2019-04-24
    09:45 - 11:15 wöchentlich
    50.34 Raum -120
    50.34 INFORMATIK, Kollegiengebäude am Fasanengarten


    2019-05-08
    09:45 - 11:15 wöchentlich
    50.34 Raum -120
    50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

    2019-05-15
    09:45 - 11:15 wöchentlich
    50.34 Raum -120
    50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

    2019-05-22
    09:45 - 11:15 wöchentlich
    50.34 Raum -120
    50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

    2019-05-29
    09:45 - 11:15 wöchentlich
    50.34 Raum -120
    50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

    2019-06-05
    09:45 - 11:15 wöchentlich
    50.34 Raum -120
    50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

    2019-06-12
    09:45 - 11:15 wöchentlich
    50.34 Raum -120
    50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

    2019-06-19
    09:45 - 11:15 wöchentlich
    50.34 Raum -120
    50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

    2019-06-26
    09:45 - 11:15 wöchentlich
    50.34 Raum -120
    50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

    2019-07-03
    09:45 - 11:15 wöchentlich
    50.34 Raum -120
    50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

    2019-07-10
    09:45 - 11:15 wöchentlich
    50.34 Raum -120
    50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

    2019-07-17
    09:45 - 11:15 wöchentlich
    50.34 Raum -120
    50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

    2019-07-24
    09:45 - 11:15 wöchentlich
    50.34 Raum -120
    50.34 INFORMATIK, Kollegiengebäude am Fasanengarten


  • lecturer: Prof. Dr. Mehdi Baradaran Tahoori
  • sws: 2
  • lv-no.: 24637
Prerequisites

Basic knowledge in "Digitaltechnik" and "Rechnerorganisation" is helpful

Content of teaching

Testing of digital circuits plays a critical role during the design and manufacturing cycles. It also ensure the quality of parts shipped to the customers. Test generation and design for testability are integral parts of automated design flow of all electronics products. The objective of this course is to provide the foundations for developing test methods for digital systems and provides the techniques necessary to practice design for testability.

This course encompasses the theoretical and practical aspects of digital systems testing and the design of easily testable circuits. Topics include Introduction to Testing (testing definition, types of test, automatic test equipments, test economics, and quality models), Failures and Errors (definitions, failure modes, failure mechanisms, reliability defects), Faults (fault models, stuck-at faults, bridging faults, timing faults, transistor-level faults, functional-level faults, effectiveness of different fault models based on real data), Logic and Fault Simulation (fault equivalence and fault collapsing, true-value simulation, fault simulation algorithms, statistical methods), Test Generation for Combinational Circuits (algebraic methods, path-tracing (D-alg, PODEM, FAN), testability metrics, test file compression), Digital Design-For-Testability and Internal Scan Design (ad-hoc methods, scan architectures, scan-based test methodology).

For further information: http://cdnc.itec.kit.edu/

Workload

2 SWS / 3 ECTS

Aim

The objective of this course is to provide the basic techniques for testing digital circuits.

Exam description

Die Erfolgskontrolle wird in der Modulbeschreibung erläutert.