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Dr.-Ing. Sarath Mohanachandran Nair

  • Dependable Computing

Short Bio

Sarath Mohanachandran Nair was born in Cherthala, India in the year 1985. He completed his Bachelors degree in Electrical and Electronics Engineering from National Institute of Technology (NIT) Calicut, India in 2007. From 2007-2011, he worked for Philips Healthcare, Bangalore developing software for the Computed Tomography (CT) modality. He then joined the Indian Institute of Technology (IIT) Bombay, India for his Masters in Microelectronics and VLSI, graduating in 2014. He then joined Samsung Semiconductor India Research, Bangalore where he was a hardware engineer for around 2 years working for the Library IP group. Since March 2016, he is working as a PhD student at the Chair of Dependable Nano Computing (CDNC) group of Prof. Mehdi Tahoori at Karlsruhe Institute of Technology.

Publications:

17. R. Bishnoi, L. Wu, M. Fieback, C. Münch, S. Mohanachandran Nair, M. Tahoori, Y. Wang, H. Li and S. Hamdioui, "Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis" in proceedings of VLSI Test Symposium (VTS), 2020, USA. (Invited Paper)

16. S. Mohanachandran Nair, C. Münch, and M. B. Tahoori, "Defect Characterization and Test Generation for Spintronic-based Compute-In-Memory", in Proceedings of the European Test Symposium (ETS), 2020, Estonia. (Best Paper Candidate)

15. S. Mohanachandran Nair, R. Bishnoi, M.B. Tahoori, H. Zahedmanesh, K. Croes, K. Garello, G. Sankar Kar, and F. Catthoor, "Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects", in International Reliability Physics Symposium (IRPS), 2020, USA.

14. S. Mohanachandran Nair, R. Bishnoi, and M.B. Tahoori, "Mitigating Read Failures in STT-MRAM", in proceedings of VLSI Test Symposium (VTS), 2020, USA. (Best Paper Candidate)

13. M.B. Tahoori, S. Mohanachandran Nair, R. Bishnoi, L. Torres, G. Partigeon, G. DiPendina, and G. Prenat, "A Universal Spintronic Technology Based on Multifunctional Standardized Stack", in proceedings of Design, Automation & Test in Europe (DATE), 2020, France.

12. S. Mohanachandran Nair, R. Bishnoi, A. Vijayan, and M.B. Tahoori, "Dynamic Faults based Hardware Trojan Design in STT-MRAM", in proceedings of Design, Automation & Test in Europe (DATE), 2020, France.

11. S. Ben Dodo, R. Bishnoi, S. Mohanachandran Nair, M.B. Tahoori, "A Novel Spintronics Memory PUF for Resilience Against Cloning Counterfeit", in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2019.

10. S. Mohanachandran Nair, R. Bishnoi, M.B. Tahoori, H.Grigoryan, G.Tshagharyan, "Variation-Aware Fault Modeling and Test Generation for STT-MRAM", in proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), 2019, Greece. (Invited Paper)

9. S. Mohanachandran Nair, R. Bishnoi, M. B. Tahoori, "A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM", in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2019.

8. S. Mohanachandran Nair, R. Bishnoi, M.B. Tahoori, H. Zahedmanesh, K. Croes, K. Garello, G. Sankar Kar, and F. Catthoor, "Variation-aware physics based electromigration modeling and experimental calibration for VLSI interconnects", in International Reliability Physics Symposium (IRPS), 2019, USA.

 

7. S. Mohanachandran Nair, R. Bishnoi, M.B. Tahoori, G. Tshagharyan, H. Grigoryan, and G. Harutyunyan, "Defect Injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM", In Proceedings of International Test Conference (ITC), 2018, USA.

 

6. M.B. Tahoori, S. Mohanachandran Nair, R. Bishnoi, S. SENNI, J. Mohdad, F. Mailly, L. Torres, P. Benoit, A. Gamatie, P. Nouet, K. Jabeur, P. Vanhauwaert, A. Atitoaie, I. Firastrau, G. Di Pendina, and G. Prenat, "Using Multifunctional Standardized Stack as Universal Spintronic Technology for IoT", in proceedings of Design, Automation & Test in Europe (DATE), 2018, Germany.​

5. S. Mohanachandran Nair, R. Bishnoi, and M. B. Tahoori, "Parametric Failure Modeling and Yield Analysis for STT-MRAM",  in proceedings of Design, Automation & Test in Europe (DATE), 2018, Germany.

4. N. Sayed, S. Mohanachandran Nair, R. Bishnoi, and M.B. Tahoori, "Process Variation and Temperature Aware Adaptive Scrubbing for Retention Failures in STT-MRAM", in Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2018, Korea.

3. S. Mohanachandran Nair, R. Bishnoi, M. S. Golanbari, F. Oboril, F. Hameed, and M. B. Tahoori, "VAET-STT: A Variation Aware STT-MRAM Analysis and Design Space Exploration Tool", in IEEE Transcactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017.

2. M.B. Tahoori, S.M. Nair, R. Bishnoi, S. Senni, J. Mohdad, F. Mailly, L. Torres, P. Benoit, P. Nouet, R. Ma, M. Kreißig, F. Ellinger, K. Jabeur, P. Vanhauwaert, G. Di Pendina and G. Prenat, "GREAT: heteroGeneous integRated magnetic tEchnology using multifunctional standardized sTack", in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, Germany.

1. S. Mohanachandran Nair, R. Bishnoi, M. S. Golanbari, F. Oboril and M. B. Tahoori, "VAET-STT: A Variation Aware Estimator Tool for STT-MRAM based Memories", in Proceedings of Design, Automation & Test in Europe (DATE), 2017, Switzerland.