Nour Sayed received her PhD degree (Dr.-Ing.) in Computer Science from Karlsruhe Institute of Technology (KIT), Germany in 19.07.2019 under the supervision of Prof. Dr. Mehdi B. Tahoori. She is currently a postdoctoral researcher at the Chair of Dependable Nano Computing (CDNC), KIT. Her main research lies in architectures for high performance, low-power and reliable computing based on emerging spintronic technologies (STT-MRAM).
Mrs. Sayed received her B.Sc. degree in Informatics Engineering from Aleppo University, Syria in 2007 with a very good note and First Rank. In 2015, she received her M.Sc. in Computer Science from KIT, Germany.
9. N. Sayed, L. Mao, R. Bishnoi and M. B. Tahoori, "Compiler-Assisted and Profiling-Based Analysis for Fast and Efficient STT-MRAM On-Chip Cache Design", in ACM Transaction on Design Automation of Electronic Systems (TODAES), 2019.
8. N. Sayed, R. Bishnoi, and M.B. Tahoori, "Fast and Reliable STT-MRAM Using Non-uniform and Adaptive Error Detecting and Correcting Scheme", in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2019
7. N. Sayed, R. Bishnoi, F. Oboril, and M. B. Tahoori, "A Cross-layer Adaptive Approach for Performance and Power Optimization in STT-MRAM", in proceedings of Design, Automation & Test in Europe (DATE), 2018, Germany.
6. N. Sayed, S. Mohanachandran Nair, R. Bishnoi, and M.B. Tahoori, "Process Variation and Temperature Aware Adaptive Scrubbing for Retention Failures in STT-MRAM", in Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2018, Korea.
5. N. Sayed, F. Oboril, A. Shirvanian, R. Bishnoi, and M.B. and Tahoori, "Exploiting STT-MRAM for Approximate Computing", in proceedings of European Test Symposium (ETS), 2017, Cyprus.
4. M. S. Golanbari, N. Sayed, M. Ebrahimi, M. H. Moshrefpour Esfahany, S. Kiamehr, and M.B. Tahoori, "Aging-Aware Coding Scheme for Memory Arrays", in proceedings of European Test Symposium (ETS), 2017, Cyprus.
3. N. Sayed, F. Oboril, R. Bishnoi, and M. B. Tahoori, "Leveraging Systematic Unidirectional Error-Detecting Codes for Fast STT-MRAM Cache", in proceedings of VLSI Test Symposium (VTS), 2017, USA.
2. N. Sayed, M. Ebrahimi, R. Bishnoi, and M. B. Tahoori, "Opportunistic Write for Fast and Reliable STT-MRAM", in Proceedings of Design, Automation & Test in Europe (DATE), 2017, Switzerland (Invited Paper).
1. M. Ebrahimi, N. Sayed, M. Rashvand, M.B. Tahoori, "Fault Injection Acceleration by Architectural Importance Sampling", in proceedings of International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), 2015, Netherlands.