Chair of Dependable Nano Computing (CDNC)

Testing Digital Systems II

  • type: lecture
  • chair: Fakultät für Informatik
  • semester: winter semester 2010/11
  • place:

    Technologiefabrik R 316.4 (Building  07.21)

  • time:

    Wednesday, 14:00 - 15:30 weekly

  • start: 20.10.2010
  • lecturer: Professor M.B. Tahoori
  • sws: 2
  • lv-no.: 24108
  • information:

    Attention: Room change! Instead of SR 301 (Building 50.34) it is R 316.4 (Building 07.21)

    No lecture on 3. November. Next lecture on 10. November.

Description

Testing of digital circuits plays a critical role during the design and manufacturing cycles. It also ensure the quality of parts shipped to the customers. Test generation and design for testability are integral parts of automated design flow of all electronics products. The objective of this course is to provide more advanced topics on testing of digital systems and complement the foundation covered in Testing Digital Systems I.

Topics include Functional and Structural Testing (design verification vectors, exhaustive test, pseudo-exhaustive test, pseudo-random testing), Essentials of Test Generation for Sequential Circuits (state-machine initialization, time-frame expansion method), Built-in Self Test (test economics of BIST, test pattern generation, output response analysis, BIST architectures), Boundary Scan (Boundary scan architectures, BS test methodology), Delay Testing (path delay test, hazard-free, robust, and non-robust delay tests, transition faults, delay test schemes), Current-Based Testing (motivation, test vectors for IDDQ, variations of IDDQ), Memory Test (memory test algorithm, memory BIST, memory repair), and DFT for System-on-Chip.