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M.Sc. Sarath Mohanachandran Nair

PhD Student
Dependable Computing
room: A.3.16.a
phone: +49 721 608 45137
fax: +49 721 608 43962
sarath nairSsn8∂kit edu


Short Bio

Sarath Mohanachandran Nair was born in Cherthala, India in the year 1985. He completed his Bachelors degree in Electrical and Electronics Engineering from National Institute of Technology (NIT) Calicut, India in 2007. From 2007-2011, he worked for Philips Healthcare, Bangalore developing software for the Computed Tomography (CT) modality. He then joined the Indian Institute of Technology (IIT) Bombay, India for his Masters in Microelectronics and VLSI, graduating in 2014. He then joined Samsung Semiconductor India Research, Bangalore where he was a hardware engineer for around 2 years working for the Library IP group. Since March 2016, he is working as a PhD student at the Chair of Dependable Nano Computing (CDNC) group of Prof. Mehdi Tahoori at Karlsruhe Institute of Technology.

Publications:

 
  1. M.B. Tahoori, S.M. Nair, R. Bishnoi, S. Senni, J. Mohdad, F. Mailly, L. Torres, P. Benoit, P. Nouet, R. Ma, M. Kreißig, F. Ellinger, K. Jabeur, P. Vanhauwaert, G. Di Pendina and G. Prenat, "GREAT: heteroGeneous integRated magnetic tEchnology using multifunctional standardized sTack", in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, Germany.

  2. S. Mohanachandran Nair, R. Bishnoi, M. S. Golanbari, F. Oboril and M. B. Tahoori, "VAET-STT: A Variation Aware Estimator Tool for STT-MRAM based Memories", in Proceedings of Design, Automation & Test in Europe (DATE), 2017, Switzerland.