As CMOS VLSI technologies enters the nanometer scales, reliability is becoming one of the major challenges for successful downscaling. The increased sensitivity of VLSI circuits to environmental and external disturbances, process variations, radiation-induced errors, and aging factors exposes these systems to an elevated rate of transient, intermittent, and permanent errors during lifetime operation. As a result, reliability screening and mitigation have to be included in the current and future nanoscale VLSI designs.
The main objective of this proposed project is to extend Design for Test (DFT) infrastructure, primarily used during manufacturing test, to Design for Reliability (DFR) during runtime. We plan to take advantage of existing built-in self-test (BIST) infrastructure, by making appropriate adjustments, to be reused during lifetime operation of VLSI systems in order to provide system monitoring to identify critical system states and perform reliability prediction. Moreover, the modified BIST infrastructure will be used to perform targeted reliability improvements. We identify, monitor, predict, and mitigate errors affecting the system reliability at different time scales to be able to handle various reliability detractors (radiation-induced soft errors, intermittent faults due to process and runtime variations, transistor aging and electromigration). Therefore, the goal is to provide runtime support for reliability screening and improvement by modifying and reusing existing DFT infrastructure with minimum costs.