The microelectronics industry will face major challenges related to power dissipation and energy consumption in the next years. Both static and dynamic consumption (already dominated by the leakage power) will soon start to limit microprocessor performance growth. Multicore processors e.g. will not be able to afford keeping more than a very small fraction of all cores active at any given moment and their scaling will soon hit a power wall. A promising way to stop this trend is integration of non-volatility as a new feature of memory caches, which would immediately minimize static power as well as paving the way towards normally-off/instant-on computing. The development of an electrically addressable NVM combining high speed and high endurance is essential to achieve these goals. Among the recent emerging memories, Spin Transfer Torque Magnetic Random Access Memory has been identified by the ITRS as the most credible candidate. However STT-MRAM still suffers from a lack of speed for cache application and from potential endurance issues due to the large current injected through the tunnel barrier for switching the magnetization.
The goal of the project is to introduce non-volatile fast memories in the core of the processors in order to develop a new class of power efficient and scalable microprocessors. To accomplish this aggressive goal, limitations of present non-volatile memories in terms of speed and endurance must be overcome and new architectures taking full benefit of these new functionalities must be developed. Would it succeed, it would imply a comprehensive modification of the memory hierarchy leading to a large reduction of power consumption and thermal dissipation. To tackle these issues the consortium will base its research on a recent discovery achieved jointly by SPINTEC and the Catalan Institute of Nanotechnology, which is called “Spin Orbit Torque” (SOT). This disruptive technology, which can be viewed as the ultimate evolution of STT, offers the same non-volatility and compliance with technological nodes below 22nm, with the addition of lower power consumption, cache-compatible high speed, and truly infinite endurance. Proof of principle has already been demonstrated on isolated cells with switching speed <0.5ns. In order to demonstrate its viability for cache, a number of identified technology roadblocks must be addressed: A magnetic stack presenting both large SOT (for write) and large Tunnel Magneto-Resistance (for read) must be developed; Writing current needs to be lowered to match advanced transistor outputs. The cell architecture must be optimized to accommodate the 3-terminal geometry. Novel system level architectures combining logic and memory must be developed, in particular with an increased granularity of the memory within the processors.
The final objective of the project is twofold: The fabrication of a SOT memory test chip, which would be benchmarked against existing and forecasted solutions (in particular state-of-the art STT-MRAM), in order to demonstrate the integrability and manufacturability of this new technology; The design and full chip simulation of a novel multicore processor integrating embedded SOT memory, in order to demonstrate the systemability of such approach.