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Rajendra Bishnoi

Dr. -Ing. Rajendra Bishnoi

Research group leader
Dependable Computing
room: A.3.16.a
phone: +49 721 608 45137
fax: +49 721 608 43962
rajendra bishnoiLgk4∂kit edu


Short Bio

Rajendra was born in Jodhpur, India in year 1981.He received his MS degree from Manipal University, India in year 2006 and done his thesis work in Purple Vision Tech, Bangalore. He has worked in Freescale as Design Engineer with Technical Solution Group (from July 2006 to Oct 2012). Mr. Bishnoi received the Ph.D. degree in Computer Science and Engineering from Karlsruhe Institute of Technology (KIT), Germany in 2017. His dissertation topic is: "Reliable Low-Power High Performance Spintronic Memories".

Patents:

1. F. Oboril, M. Tahoori, R. Bishnoi,Non-Volatile Non-Shadow Flip-Flop”,  EU Patent No: 16000198.8-1805 (pending)

 

Publications: 

24. N. Sayed, S. Mohanachandran Nair, R. Bishnoi, and M.B. Tahoori, "Process Variation and Temperature Aware Adaptive Scrubbing for Retention Failures in STT-MRAM", in Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2018, Korea.

23. S. Mohanachandran Nair, R. Bishnoi, M. S. Golanbari, F. Oboril, F. Hameed, and M. B. Tahoori, "VAET-STT: A Variation Aware STT-MRAM Analysis and Design Space Exploration Tool",in IEEE Transcactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017.

22. S. Mittal, R. Bishnoi, F. Oboril, H. Wang, M.B. Tahoori, A. Jog and J.S. Vetter, "Architecting SOT-RAM Based GPU Register File", in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, Germany.

21. M. Tahoori, S.M. Nair, R. Bishnoi, S. Senni, J. Mohdad, F. Mailly, L. Torres, P. Benoit, P. Nouet, R. Ma, M. Kreißig, F. Ellinger, K. Jabeur, P. Vanhauwaert, G. Di Pendina and G. Prenat, "GREAT: heteroGeneous integRated magnetic tEchnology using multifunctional standardized sTack", in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, Germany.

20. N. Sayed, F. Oboril, A. Shirvanian, R. Bishnoi, and M.B. and Tahoori, "Exploiting STT-MRAM for Approximate Computing", in proceedings of European Test Symposium (ETS), 2017, Cyprus.

19. N. Sayed, F. Oboril, R. Bishnoi, and M. B. Tahoori, "Leveraging Systematic Unidirectional Error-Detecting Codes for Fast STT-MRAM Cache", in proceedings of VLSI Test Symposium (VTS), 2017, USA.

18. N. Sayed, M. Ebrahimi, R. Bishnoi, and M. B. Tahoori, "Opportunistic Write for Fast and Reliable STT-MRAM", in Proceedings of Design, Automation & Test in Europe (DATE), 2017, Switzerland.

17. R. Bishnoi, F. Oboril and M.B. Tahoori, "Design of Defect and Fault Tolerant Non-Volatile Spintronic Flip-Flops", in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2017.

16. S. Mohanachandran Nair, R. Bishnoi, M. S. Golanbari, F. Oboril and M. B. Tahoori, "VAET-STT: A Variation Aware Estimator Tool for STT-MRAM based Memories", in Proceedings of Design, Automation & Test in Europe (DATE), 2017, Switzerland.

15. F. Oboril, F. Hameed, R. Bishnoi, A. Ahari, H. Naeimi and M.B. Tahoori, "Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches", International Symposium on Low Power Electronics and Design (ISLPED), 2016, USA.

14. R. Bishnoi, M. Ebrahimi, F. Oboril and M.B. Tahoori, "Improving Write Performance for STT-MRAM", IEEE Transactions on Magnetics (TMAG), 2016

13. R. Bishnoi, F. Oboril and M.B. Tahoori, "Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic Devices", in Proceedings of Great Lakes  Symposium on VLSI (GLSVLSI), 2016, USA.

12. F. Oboril, R. Bishnoi, M. Ebrahimi, M.B. Tahoori, G. Di Pendina, K. Jabeur, and G. Prenat "Spin Orbit Torque memory for non-volatile microprocessor caches", International Workshop on Emerging Memory Solutions, 2016, Germany.

11. G. Prenat, G.D. Pendina, K. Jabeur, P. Vanhauwaert, O. Boulle, M. Miron, G. Gaudin, F. Oboril, R. Bishnoi, M. Ebrahimi, M. Tahoori, K. Garello and P. Gambardella, "Ultra-Fast and High-Reliability SOT-MRAM: from Cache Replacement to Normally-off Computing", in IEEE Transactions on Multi-Scale Computing Systems (TMSCS), 2016.

10. A. Gebregiorgis, S. Kiamehr, F. Oboril, R. Bishnoi, M.B. Tahoori, "A Cross-Layer Analysis of Soft Error, Aging and Process Variation in Near Threshold Computing", in Proceedings of Design, Automation & Test in Europe (DATE), 2016, Germany.

9. R. Bishnoi, F. Oboril and M.B. Tahoori, "Fault Tolerant Non-Volatile Spintronic Flip-Flop", in Proceedings of Design, Automation & Test in Europe (DATE), 2016, Germany.

8. R. Bishnoi, F. Oboril and M.B. Tahoori, "Non-volatile Non-Shadow Flip-Flop using Spin Orbit Torque for Efficient Normally-off Computing", in Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2016, China.

7. R. Bishnoi, F. Oboril, M. Ebrahimi and M.B. Tahoori, "Self-timed Read and Write Operations in STT-MRAM", in IEEE Transactions on Very Large Scale Integration System (TVLSI), 2016.

6. M. Ebrahimi, H. Asadi, R. Bishnoi, M.B. Tahoori, ”Layout-based Modeling and Mitigation of Multiple Event Transients”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016.

5. F. Oboril, R. Bishnoi, M. Ebrahimi and M.B. Tahoori, "Evaluation of Hybrid Memory Technologies using SOT-MRAM for On-Chip Cache Hierarchy", in IEEE Transactions on Computer-Aided Design of  Integrated Circuits and Systems (TCAD), 2015.

4. R. Bishnoi, M. Ebrahimi, F. Oboril and M.B. Tahoori , "Read Disturb Fault Detection in STT-MRAM", Proceedings of International Test Conference (ITC), 2014, USA.

3. R. Bishnoi, F. Oboril, M. Ebrahimi,  and M.B. Tahoori , "Avoiding Unnecessary Write Operations in STT-MRAM for Low Power Implementation", in Proceedings of the International Symposium on Quality Electronic Design  (ISQED), 2014, USA

2. R. Bishnoi, M. Ebrahimi, F. Oboril and M.B. Tahoori , "Asynchronous Asymmetrical Write Termination (AAWT) for a Low Power STT-MRAM", in Proceedings of Design, Automation & Test in Europe (DATE), 2014, Germany.

1. R. Bishnoi, M. Ebrahimi, F. Oboril and M.B. Tahoori , "Architectural Aspects in Design and Analysis of SOT-based Memories",  in proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2014, Singapore (Invited Paper).

M.Sc. Thesis:   

“Reusable SoC Verification Environment IP” at Manipal University, India, 2006.

 

B.E. Thesis:

“Water Purification Using Embedded Controller” at Visveswaraih Technological University, India, 2003.