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Rajendra Bishnoi

Dr. -Ing. Rajendra Bishnoi

Research group leader
Dependable Computing
room: A.3.16.a
phone: +49 721 608 45137
fax: +49 721 608 43962
rajendra bishnoiJuo0∂kit edu


Short Bio

Rajendra Bishnoi received his PhD degree in Computer Science from Karlsruhe Institute of Technology (KIT), Germany, in 2017. He is currently a research lead for the MRAM group in the Chair of Dependable Nano Computing, KIT. Before joining KIT, he was a design engineer in Freescale, from 2006 to 2012, working with the Technical Solution Group in the area of memory and SoC flow. His research interests include spintronic technologies (SOT-MRAM and STT-MRAM), low-power design, neuromorphic computing and hardware security. He was a recipient of European Design & Automation Association (EDAA) Outstanding Dissertation Award for the year 2017 in the category of new directions in logic, physical design and CAD for analog/mixed-signal, nano-scale and emerging technologies.

Patents:

5. M.S. Golanbari, S. Kiamehr, R. Bishnoi, M. B. Tahoori,”Reliable Low-Power Memory-Based PUF Architecture”, 2018, (EU Patent No: 18000240.4).

4. R. Bishnoi, C. Münch, M.B. Tahoori, “Multi-Bit Non-Volatile Flip-Flop”, 2018, EU Patent No: 18000262.8.

3. R. Bishnoi, F. Oboril, and M.B. Tahoori, “Efficient Testing of a Magnetic Memory Circuit”, 2017, EU Patent No: 17001784.2-1203.

2. R. Bishnoi, F. Oboril, and M.B. Tahoori, “Magnetic Probe Based Test Methodology for Spintronic Technologies”, 2017, EU Patent No: 17401042.1-1568.

1. R. Bishnoi, F. Oboril, and M.B. Tahoori, “Non-Volatile Non-Shadow Flip-Flop”, 2016, EU Patent No: 16000198.8-1805.

 

Publications: 

40. S. Mohanachandran Nair, R. Bishnoi, M.B. Tahoori, H. Zahedmanesh, K. Croes, K. Garello, G. Sankar Kar, and F. Catthoor, "Variation-aware physics based electromigration modeling and experimental calibration for VLSI interconnects", in International Reliability Physics Symposium (IRPS), 2019, USA.

39. C. Münch, R. Bishnoi, and M.B. Tahoori, "Reliable In-Memory Neuromorphic Computing using Spintronics", Asia and South Pacific Design Automation Conference (ASP-DAC), 2019, Japan (Invited paper).

38. F. Rasheed, M. Hefenbrock, R. Bishnoi, M. Beigl, J. Aghassi-Hagmann and M.B. Tahoori, "Predictive Modeling and Design Automation of Inorganic Printed Electronics", in proceedings of Design, Automation & Test in Europe (DATE), 2019, Italy (Invited paper).

37. A. T. Erozan, R. Bishnoi, J. Aghassi-Hagmann and M.B. Tahoori, "Inkjet Printed True Random Number Generator based on Additive Resistor Tuning",  in proceedings of Design, Automation & Test in Europe (DATE), 2019, Italy.

36. G. Tshagharyan, G. Harutyunyan, Y. Zorian, A. Gebregiorgis, M.S. Golanbari, R. Bishnoi, and M.B. Tahoori, "Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications", In Proceedings of International Test Conference (ITC), 2018, USA.

35. S. Mohanachandran Nair, R. Bishnoi, M.B. Tahoori, G. Tshagharyan, H. Grigoryan, and G. Harutyunyan, "Defect Injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM", In Proceedings of International Test Conference (ITC), 2018, USA.

34. A. T. Erozan, G.C. Marques, M.S. Golanbari, R. Bishnoi, S. Dehm, J. Aghassi-Hagmann, M. B. Tahoori, "Inkjet Printed EGFET-based Physical Unclonable Function - Design, Evaluation, and Fabrication​", in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2018

33. A. Gebregiorgis, R. Bishnoi, and M.B. Tahoori, "A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device Approach", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018.

32. M. S. Golanbari, S. Kiamehr, R. Bishnoi, and M. B. Tahoori, "Reliable Memory PUF Design for Low-Power Applications," in Proceedings of the International Symposium on Quality Electronic Design (ISQED), 2018, USA.

31. A. T. Erozan, M. S. Golanbari, R. Bishnoi,  J. Aghassi-Hagmann, and M. B. Tahoori, "Design and Evaluation of Physical Unclonable Function for Inorganic Printed Electronics",  in proceedings of the International Symposium on Quality Electronic Design (ISQED), 2018, USA. 

30. A. Gebregiorgis, R. Bishnoi, and M.B. Tahoori, "Spintronic Normally-off Heterogeneous System-on-Chip Design",  in proceedings of Design, Automation & Test in Europe (DATE), 2018, Germany.

29. M.B. Tahoori, S. Mohanachandran Nair, R. Bishnoi, S. SENNI, J. Mohdad, F. Mailly, L. Torres, P. Benoit, A. Gamatie, P. Nouet, K. Jabeur, P. Vanhauwaert, A. Atitoaie, I. Firastrau, G. Di Pendina, and G. Prenat, "Using Multifunctional Standardized Stack as Universal Spintronic Technology for IoT", in proceedings of Design, Automation & Test in Europe (DATE), 2018, Germany.

​28. C. Münch, R. Bishnoi, and M.B. Tahoori, "Multi-Bit Non-Volatile Spintronic Flip-Flop",  in proceedings of Design, Automation & Test in Europe (DATE), 2018, Germany. (Best Paper Candidate)

27. S. Mohanachandran Nair, R. Bishnoi, and M. B. Tahoori, "Parametric Failure Modeling and Yield Analysis for STT-MRAM",  in proceedings of Design, Automation & Test in Europe (DATE), 2018, Germany.

26. N. Sayed, R. Bishnoi,  F. Oboril, and M. B. Tahoori, "A Cross-layer Adaptive Approach for Performance and Power Optimization in STT-MRAM", in proceedings of Design, Automation & Test in Europe (DATE), 2018, Germany.

25. N. Sayed, S. Mohanachandran Nair, R. Bishnoi, and M.B. Tahoori, "Process Variation and Temperature Aware Adaptive Scrubbing for Retention Failures in STT-MRAM", in Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2018, Korea.

24. S. Mohanachandran Nair, R. Bishnoi, M. S. Golanbari, F. Oboril, F. Hameed, and M. B. Tahoori, "VAET-STT: A Variation Aware STT-MRAM Analysis and Design Space Exploration Tool",in IEEE Transcactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017.

23. R Bishnoi, "Reliable Low-Power High Performance Spintronic Memories", PhD Thesis, 2017.

22. S. Mittal, R. Bishnoi, F. Oboril, H. Wang, M.B. Tahoori, A. Jog and J.S. Vetter, "Architecting SOT-RAM Based GPU Register File", in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, Germany.

21. M. Tahoori, S.M. Nair, R. Bishnoi, S. Senni, J. Mohdad, F. Mailly, L. Torres, P. Benoit, P. Nouet, R. Ma, M. Kreißig, F. Ellinger, K. Jabeur, P. Vanhauwaert, G. Di Pendina and G. Prenat, "GREAT: heteroGeneous integRated magnetic tEchnology using multifunctional standardized sTack", in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, Germany.

20. N. Sayed, F. Oboril, A. Shirvanian, R. Bishnoi, and M.B. and Tahoori, "Exploiting STT-MRAM for Approximate Computing", in proceedings of European Test Symposium (ETS), 2017, Cyprus.

19. N. Sayed, F. Oboril, R. Bishnoi, and M. B. Tahoori, "Leveraging Systematic Unidirectional Error-Detecting Codes for Fast STT-MRAM Cache", in proceedings of VLSI Test Symposium (VTS), 2017, USA.

18. N. Sayed, M. Ebrahimi, R. Bishnoi, and M. B. Tahoori, "Opportunistic Write for Fast and Reliable STT-MRAM", in Proceedings of Design, Automation & Test in Europe (DATE), 2017, Switzerland.

17. R. Bishnoi, F. Oboril and M.B. Tahoori, "Design of Defect and Fault Tolerant Non-Volatile Spintronic Flip-Flops", in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2017.

16. S. Mohanachandran Nair, R. Bishnoi, M. S. Golanbari, F. Oboril and M. B. Tahoori, "VAET-STT: A Variation Aware Estimator Tool for STT-MRAM based Memories", in Proceedings of Design, Automation & Test in Europe (DATE), 2017, Switzerland.

15. F. Oboril, F. Hameed, R. Bishnoi, A. Ahari, H. Naeimi and M.B. Tahoori, "Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches", International Symposium on Low Power Electronics and Design (ISLPED), 2016, USA.

14. R. Bishnoi, M. Ebrahimi, F. Oboril and M.B. Tahoori, "Improving Write Performance for STT-MRAM", IEEE Transactions on Magnetics (TMAG), 2016

13. R. Bishnoi, F. Oboril and M.B. Tahoori, "Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic Devices", in Proceedings of Great Lakes  Symposium on VLSI (GLSVLSI), 2016, USA.

12. F. Oboril, R. Bishnoi, M. Ebrahimi, M.B. Tahoori, G. Di Pendina, K. Jabeur, and G. Prenat "Spin Orbit Torque memory for non-volatile microprocessor caches", International Workshop on Emerging Memory Solutions, 2016, Germany.

11. G. Prenat, G.D. Pendina, K. Jabeur, P. Vanhauwaert, O. Boulle, M. Miron, G. Gaudin, F. Oboril, R. Bishnoi, M. Ebrahimi, M. Tahoori, K. Garello and P. Gambardella, "Ultra-Fast and High-Reliability SOT-MRAM: from Cache Replacement to Normally-off Computing", in IEEE Transactions on Multi-Scale Computing Systems (TMSCS), 2016.

10. A. Gebregiorgis, S. Kiamehr, F. Oboril, R. Bishnoi, M.B. Tahoori, "A Cross-Layer Analysis of Soft Error, Aging and Process Variation in Near Threshold Computing", in Proceedings of Design, Automation & Test in Europe (DATE), 2016, Germany.

9. R. Bishnoi, F. Oboril and M.B. Tahoori, "Fault Tolerant Non-Volatile Spintronic Flip-Flop", in Proceedings of Design, Automation & Test in Europe (DATE), 2016, Germany.

8. R. Bishnoi, F. Oboril and M.B. Tahoori, "Non-volatile Non-Shadow Flip-Flop using Spin Orbit Torque for Efficient Normally-off Computing", in Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2016, China.

7. R. Bishnoi, F. Oboril, M. Ebrahimi and M.B. Tahoori, "Self-timed Read and Write Operations in STT-MRAM", in IEEE Transactions on Very Large Scale Integration System (TVLSI), 2016.

6. M. Ebrahimi, H. Asadi, R. Bishnoi, M.B. Tahoori, ”Layout-based Modeling and Mitigation of Multiple Event Transients”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016.

5. F. Oboril, R. Bishnoi, M. Ebrahimi and M.B. Tahoori, "Evaluation of Hybrid Memory Technologies using SOT-MRAM for On-Chip Cache Hierarchy", in IEEE Transactions on Computer-Aided Design of  Integrated Circuits and Systems (TCAD), 2015.

4. R. Bishnoi, M. Ebrahimi, F. Oboril and M.B. Tahoori , "Read Disturb Fault Detection in STT-MRAM", Proceedings of International Test Conference (ITC), 2014, USA.

3. R. Bishnoi, F. Oboril, M. Ebrahimi,  and M.B. Tahoori , "Avoiding Unnecessary Write Operations in STT-MRAM for Low Power Implementation", in Proceedings of the International Symposium on Quality Electronic Design  (ISQED), 2014, USA

2. R. Bishnoi, M. Ebrahimi, F. Oboril and M.B. Tahoori , "Asynchronous Asymmetrical Write Termination (AAWT) for a Low Power STT-MRAM", in Proceedings of Design, Automation & Test in Europe (DATE), 2014, Germany.

1. R. Bishnoi, M. Ebrahimi, F. Oboril and M.B. Tahoori , "Architectural Aspects in Design and Analysis of SOT-based Memories",  in proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2014, Singapore (Invited Paper).