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Shengcheng Wang

M.Sc. Eng. Shengcheng Wang

PhD Student
Dependable Computing
room: A.3.20
phone: +49 721 608 44859
fax: +49 721 608 43962
shengcheng wangDji8∂kit edu


Short Bio

Shengcheng Wang received his Bachelor degree in Microelectronics at Nankai University, China, in 2007. After four years study there, he was admitted to the Department of Microelectronics at Peking University, China. In the Novel Device Research Group at Peking University, he conducted his Masters research with Prof. Xiaoyan Liu, and narrowed his academic interest down to the Negative Bias Temperature Instability (NBTI) issues in nanoscale devices. He started working as a PhD student in the CDNC group of Prof. Tahoori at Karlsruhe Institute of Technology in October 2012.


 

Publications

10. S. Wang, Z, Sun, Y, Cheng, S.X.-D Tan, and M. B. Tahoori, "Leveraging Recovery Effect to Reduce Electromigration Degradation in Power/Ground TSV", In Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017, USA (Invited Paper).

9. S. Wang, and M.B. Tahoori, "Electromigration-aware Local-Via Allocation in Power/Ground TSVs of 3D ICs", In IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2017.

8. S. Wang, H. Zaho, S.X.-D Tan, and M. B. Tahoori, "Recovery-aware Proactive TSV Repair for Electromigration in 3D ICs", in Proceedings of Design, Automation & Test in Europe (DATE), 2017, Switzerland.

7. S. Wang, R. Wang, K. Chakrabarty, and M. B. Tahoori, "Multicast Test Architecture and Test Scheduling for Interposer-based 2.5D ICs", in Asian Test Symposium (ATS), 2016, Japan (Invited Paper).

6. S. Wang, K, Chakrabarty, and M.B. Tahoori, "Thermal-aware TSV Repair for Electromigration in 3D ICs", in Proceedings of Design, Automation & Test in Europe (DATE), 2016, Germany.

5. S. Wang, K. Chakrabarty, and M.B. Tahoori, "Novel Spare TSV Allocation for 3D-ICs Considering Defect Clustering Effect", in Proceedings of International Conference on Computer-Aided Design (ICCAD), 2015, USA (Best Paper Award).

4. S. Wang, F.  Firouzi, F. Oboril, and M.B. Tahoori, "Deadspace-aware Power/Ground TSV Planning in 3D Floorplanning", in Proceedings of International Conference on Integrated Circuit Design and Technology (ICICDT), 2015, Belgium (Invited Paper).

3. S. Wang, F.  Firouzi, F. Oboril, and M.B. Tahoori, "Stress-aware P/G TSV Planning in 3D-ICs", in Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2015, Japan.

2. S. Wang, F. Firouzi, F. Oboril, and M.B. Tahoori, "P/G TSV Planning for IR-drop Reduction in 3D-ICs", in Proceedings of Design, Automation & Test in Europe (DATE), 2014, Germany.

1. S. Wang, G. Du, X. Liu, "An Analytical Model for Negative Bias Temperature Instability," in Proceedings of International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), 2010, China.