Short Bio

Fabian Oboril received his Diplom (Dipl.-Math. techn.) in Technomathematics and Ph.D. (Dr.-Ing.) in Computer Science from the Karlsruhe Institute of Technology (KIT) Germany in 2010 and 2015, respectively. His dissertation addresses the reliability challenge of accelerated transistor aging in nanoscale technology nodes. Fabian Oboril is currently a post-doctoral research assistant at the Chair of Dependable Nano Computing (CDNC) at KIT.

Since 2015, Fabian Oboril is the leader of the MRAM research group at CDNC focusing on emering non-volatile spintronic devices and architectures.

Education:

January 2015:       Dr.-Ing. (Ph.D.) in Computer Science, KIT, Karlsruhe, Germany
                               Dissertation: "Cross-Layer Approaches for an Aging-Aware Design of Nanoscale Microprocessors". (PDF)
                               Advisor: Prof. Mehdi Tahoori,     Co-Advisor: Prof. Jörg Henkel
                               The dissertation received the IEEE TTTC’s E. J. McCluskey Best Doctoral Thesis Award 2015
Mai 2010:               Dipl.-Math. techn., KIT, Karlsruhe, Germany
                               Thesis: "Parallele 3D Mehrgitter-Methoden auf der STI Cell BE Architektur"

Research Interests:

• Reliability issues in nano era and fault tolerant computing.
• High Performance Computing & Multicore Programming.
• Efficient usage of heterogeneous architectures in the context of High Performance Computing.
• Non-Volatile emerging memory technologies such as STT-MRAM.

Projects:

• GREAT: Heterogeneous Integrated Magnetic Technology using Multifunctional Standardized Stack
• Development of the micro-architectural framework ExtraTime that can model Power, Temperature and Aging of processor components
• DFG SPP-1500 Dependable Embedded System with focus on "Cross-layer Modeling and Mitigation of Aging Effects in Embedded Systems"
• spOt: spin Orbit torque memory for cache & multicore processor applications

Teaching:

• Rechnerorganisation
• Digitaltechnik

Patents:

1. F. Oboril, M. Tahoori, R. Bishnoi, “Non-Volatile Non-Shadow Flip-Flop”,  EU Patent No: 16000198.8-1805 (pending)

Publications:

2017

51. S. Mohanachandran Nair, R. Bishnoi, M. S. Golanbari, F. Oboril and M. B. Tahoori, "VAET-STT: A Variation Aware Estimator Tool for STT-MRAM based Memories", in Proceedings of Design, Automation & Test in Europe (DATE), 2017, Switzerland.

2016

50. D. R. E. Gnad, F. Oboril, S. Kiamehr, M. B. Tahoori, "Analysis of Transient Voltage Fluctuations in FPGAs", International Conference on Field-Programmable Technology (FPT), 2016, China.

49. M. S. Golanbari, A. Gebregiorgis, F. Oboril, S. Kiamehr, and M. B. Tahoori, "A Cross-Layer Approach for Resiliency and Energy Efficiency in Near Threshold Computing", in proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2016, USA (Invited paper).

48. A. Vijayan, S. Kiamehr, F. Oboril, K. Chakrabarty, and M.B. Tahoori, "Workload-aware Static Aging Monitoring of Timing Critical Flip-flops", in Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2017, Japan.

47. Fabian Oboril, Azadeh Shirvanian and M.B. Tahoori, "Fault tolerant approximate computing using emerging non-volatile spintronic memories", in proceedings of 34st VLSI Test Symposium (VTS), 2016, USA.

46. F. Oboril, F. Hameed, R. Bishnoi, A. Ahari, H. Naeimi and M.B. Tahoori, "Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches", International Symposium on Low Power Electronics and Design (ISLPED), 2016, USA.

45. A. Gebregiorgis, M. Golanbari, S. Kiamehr, F. Oboril and M.B. Tahoori, "Maximizing Energy Efficiency in NTC by Variation-Aware Microprocessor Pipeline Optimization", International Symposium on Low Power Electronics and Design (ISLPED), 2016, USA.

44. F. Oboril, A. Shirvanian and M.B. Tahoori, "Fault Tolerant Approximate Computing Using Emerging Non-Volatile Spintronic Memories", IEEE 34th VLSI Test Symposium (VTS), 2016, USA.

43. R. Bishnoi, M. Ebrahimi, F. Oboril and M.B. Tahoori, "Improving Write Performance for STT-MRAM", IEEE Transactions on Magnetics, 2016

42. R. Bishnoi, F. Oboril and M.B. Tahoori, "Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic Devices", in Proceedings of Great Lakes  Symposium on VLSI (GLSVLSI), 2016, USA.

41. F. Oboril, R. Bishnoi, M. Ebrahimi, M.B. Tahoori, G. Di Pendina, K. Jabeur, and G. Prenat "Spin Orbit Torque memory for non-volatile microprocessor caches", International Workshop on Emerging Memory Solutions, 2016, Germany.

40. F. Oboril, and M. B. Tahoori "Cross-Layer Approaches for an Aging-Aware Design Space Exploration of Microprocessors", Workshop on Early Reliability Modelling for Aging and Variability in Silicon Systems (ERMAVSS), 2016, Germany.

39. G. Prenat, G.D. Pendina, K. Jabeur, P. Vanhauwaert, O. Boulle, M. Miron, G. Gaudin, F. Oboril, R. Bishnoi, M. Ebrahimi, M. Tahoori, K. Garello and P. Gambardella, "Ultra-Fast and High-Reliability SOT-MRAM: from Cache Replacement to Normally-off Computing", in IEEE Transactions on Multi-Scale Computing Systems (TMSCS), 2016.

38. A. Gebregiorgis, F. Oboril, M.B. Tahoori, and S. Hamdioui, "Instruction Cache Aging Mitigation Through Instruction Set Encoding", in Proceedings of the International Symposium on Quality Electronic Design (ISQED), 2016, USA.

37. R. Bishnoi, F. Oboril and M.B. Tahoori, "Fault Tolerant Non-Volatile Spintronic Flip-Flop", in Proceedings of Design, Automation & Test in Europe (DATE), 2016, Germany.

36. A. Gebregiorgis, S. Kiamehr, F. Oboril, R. Bishnoi, M.B. Tahoori, "A Cross-Layer Analysis of Soft Error, Aging and Process Variation in Near Threshold Computing", in Proceedings of Design, Automation & Test in Europe (DATE), 2016, Germany.

35. R. Bishnoi, F. Oboril and M.B. Tahoori, "Self-timed Read and Write Operations in STT-MRAM", in IEEE Transaction on Very Large Scale Integration Systems (TVLSI), 2016. 

34. R. Bishnoi, F. Oboril and M.B. Tahoori , "Non-Volatile Non-Shadow Flip-Flop using Spin Orbit Torque for Efficient Normally-off Computing", in Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2016, China.

2015

33. A. Shirvanian, F. Oboril, and M.B. Tahoori, "Leveraging Approximate Computing for Improving STT-MRAM Write Efficiency", in Approximate Computing Workshop, 2015, Germany.

32. F. Oboril, "Cross-Layer Approaches for an Aging-Aware Design of Nanoscale Microprocessors", in International Test Conference  (ITC), 2015, USA.

31. A. Ahari, M. Ebrahimi, F. Oboril and M.B. Tahoori, "Improving Reliability, Performance, and Energy Efficiency of STT-MRAM with Dynamic Write Latency", in International Conference on Computer Design (ICCD), 2015, USA.

30. M. Glaß, H. Aliee, L. Chen, M. Ebrahimi, F. Khosravi, V. Kleeberger, A. Listl, D. Müller-Gritchneder, F. Oboril, U. Schlichtmann, M.B. Tahoori, J. Teich, N. Wehn, C. Weis, "Application-aware cross-layer reliability analysis and optimization", in it - Information Technology, 2015.

29. S. Wang, F. Firouzi, F. Oboril, M.B. Tahoori, "Deadspace-aware Power/Ground TSV Planning in 3D Floorplanning", in Proceedings of International Conference on Integrated Circuit Design and Technology (ICICDT), 2015, Belgium (Invited Paper). 

28. F. Oboril, and M.B. Tahoori, "Exploiting Instruction Set Encoding for Aging-Aware Microprocessor Design", in ACM Transactions on Design Automation of Electronic Systems (TODAES), 2015.

27. F. Oboril, "Cross-Layer Approaches for an Aging-Aware Design of Nanoscale Microprocessors", Dissertation, 2015. (PDF)

26. A. Banaiyanmofrad, M. Ebrahimi, F. Oboril, M.B. Tahoori, N. Dutt, "Protecting Caches Against Multiple Bit Upsets Using Embedded Erasure Coding", in proceedings of European Test Symposium (ETS), 2015, Romania.

25. F. Oboril, R. Bishnoi, M. Ebrahimi and M.B. Tahoori, "Evaluation of Hybrid Memory Technologies using SOT-MRAM for On-Chip Cache Hierarchy", in IEEE Transactions on Computer-Aided Design of  Integrated Circuits and Systems (TCAD), 2015. (PDF)

24. F. Oboril, J. Ewert, and M. B. Tahoori, “High-Resolution Online Power Monitoring for Modern Microprocessors,” in Proceedings of  Design, Automation & Test in Europe (DATE), 2015, France. (PDF)

23. F. Oboril, M. Ebrahimi, S. Kiamehr,  M.B. Tahoori, "Cross-Layer Resilient System Design Flow", in Proceedings of theInternational Symposium on Circuits and Systems (ISCAS), 2015, Portugal.

22. S. Wang, F.  Firouzi, F. Oboril, M.B. Tahoori, Stress-aware P/G TSV Planning in 3D-ICs", in Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2015, Japan.

21. A. Gebregiorgis, M. Ebrahimi, S. Kiamehr, F. Oboril, S. Hamdioui, M.B. Tahoori, "Aging Mitigation in Memory Arrays Using Self-controlled Bit-flipping Technique", in Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2015, Japan. (PDF)

2014

20. R. Bishnoi, M. Ebrahimi, F. Oboril and M.B. Tahoori , "Read Disturb Fault Detection in STT-MRAM", Proceedings of International Test Conference (ITC), 2014, USA. (PDF)

19. F. Oboril and M. Tahoori, "Aging-Aware Design of Microprocessor Instruction Pipelines", in IEEE Transactions on Computer-Aided Design of  Integrated Circuits and Systems (TCAD), 2014. (PDF)

18. R. Bishnoi, F. Oboril, M. Ebrahimi,  and M.B. Tahoori , "Avoiding Unnecessary Write Operations in STT-MRAM for Low Power Implementation", in Proceedings of the International Symposium on Quality Electronic Design  (ISQED), 2014, USA. (PDF)

17. F. Oboril and M.B. Tahoori , "Cross-Layer Approaches for Aging-Aware Design of Nanoscale Microprocessors", Proceedings of Design, Automation & Test in Europe (DATE), 2014, Germany (PhD forum paper).

16. S. Wang, F. Firouzi, F. Oboril, M.B. Tahoori, " P/G TSV Planning for IR-drop Reduction in 3D-ICs", in Proceedings of Design, Automation & Test in Europe (DATE), 2014, Germany. (PDF)

15. R. Bishnoi, M. Ebrahimi, F. Oboril and M.B. Tahoori , "Asynchronous Asymmetrical Write Termination (AAWT) for a Low Power STT-MRAM", in Proceedings of Design, Automation & Test in Europe (DATE), 2014, Germany. (PDF)

14. R. Bishnoi, M. Ebrahimi, F. Oboril and M.B. Tahoori , "Architectural Aspects in Design and Analysis of SOT-based Memories",  in proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2014, Singapore (Invited Paper). (PDF)

13. F. Oboril, M.B. Tahoori, "ArISE: Aging-aware Instruction Set Encoding for Lifetime Improvement", in proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2014, Singapore. (PDF)

2013

12. F. Oboril, F. Firouzi, S. Kiamehr, and M. B. Tahoori, "Negative Bias Temperature Instability-Aware Instruction Scheduling: A Cross-Layer Approach", Journal of Low Power Electron. 9, 2013.

11. M. Ebrahimi, F. Oboril, S. Kiamehr, M.B. Tahoori, "Aging-aware Logic Synthesis", in proceedings of the International conference on Computer-Aided Design (ICCAD), 2013, USA. (PDF)

10. F. Oboril, I. Sagar, M.B. Tahoori,  "A-SOFT-AES: Self-Adaptive Software-Implemented Fault-Tolerance for AES", in proceedings of International On-Line Testing Symposium (IOLTS), 2013, Greece. (PDF)

9. F. Oboril, M.B. Tahoori, "MTTF-Balanced Pipeline Design",  in proceedings of Design, Automation & Test in Europe (DATE), 2013, France (Best Paper Candidate). (PDF)

2012

8. F. Oboril, M.B. Tahoori, "ExtraTime: Eine Mikroarchitektur-Simulationsumgebung zur Modellierung, Analyse und Linderung von Alterungseffekten", GMM Mechatronik, 2012 (invited paper). (PDF)

7. F. Oboril, F. Firouzi, S. Kiamehr, M.B. Tahoori, "Reducing NBTI-induced Processor Wearout by Exploiting the Timing Slack of Instructions", in proceedings of International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2012, Finland. (PDF)

6. F. Oboril, F. Firouzi, S. Kiamehr, M.B. Tahoori, "Impact of Instruction Delay on Processor Wearout", in proceedings of the Workshop on Processor Verification, Test and Debug (IWPVTD), 2012, France.

5. F. Oboril and M.B. Tahoori, "ExtraTime: Modeling and Analysis of Wearout due to Transistor Aging at Microarchitecture-Level", in proceedings of  Dependable Systems and Networks (DSN), 2012, USA. (PDF)

4. F. Oboril and M.B. Tahoori, "Reducing Wearout in Embedded Processors using Proactive Fine-Grain Dynamic Runtime Adaptation", in proceedings of European Test Symposium (ETS), 2012, France. (PDF)

2011

3. F. Oboril, M.B. Tahoori, V. Heuveline, D. Lukarski, and J.P. Weiss, "Numerical Defect Correction as an Algorithm-Based Fault Tolerance Technique for Iterative Solvers", in proceedings of the 17th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), 2011. (PDF)

2. F. Oboril and M.B. Tahoori, "ExtraTime: A Framework for Exploration of Clock and Power Gating for BTI and HCI Aging Mitigation", in proceedings of Zuverlässigkeit und Entwurf (ZuE), 2011, Germany (Best Paper Award). (PDF)

2010

1. F. Oboril, V. Heuveline, J.P. Weiss, "Parallel 3D Multigrid Methods on the STI Cell BE Architecture", in
proceedings of the conference for junior researchers facing the multicore challenge, 2010, Germany.