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Testing Digital Systems I

Testing Digital Systems I
type: Vorlesung (V)
semester: SS 2015
time: 2015-04-14
11:30 - 13:00 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten


2015-04-21
11:30 - 13:00 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2015-04-28
11:30 - 13:00 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2015-05-05
11:30 - 13:00 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2015-05-12
11:30 - 13:00 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2015-05-19
11:30 - 13:00 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2015-05-26
11:30 - 13:00 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2015-06-02
11:30 - 13:00 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2015-06-09
11:30 - 13:00 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2015-06-16
11:30 - 13:00 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2015-06-23
11:30 - 13:00 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2015-06-30
11:30 - 13:00 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2015-07-07
11:30 - 13:00 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten

2015-07-14
11:30 - 13:00 wöchentlich
50.34 Raum -101 50.34 INFORMATIK, Kollegiengebäude am Fasanengarten


lecturer: Prof.Dr. Mehdi Baradaran Tahoori
sws: 2
lv-no.: 24637
DescriptionTesting of digital circuits plays a critical role during the design and manufacturing cycles. It also ensure the quality of parts shipped to the customers. Test generation and design for testability are integral parts of automated design flow of all electronics products. The objective of this course is to provide the foundations for developing test methods for digital systems and provides the techniques necessary to practice design for testability.

This course encompasses the theoretical and practical aspects of digital systems testing and the design of easily testable circuits. Topics include Introduction to Testing (testing definition, types of test, automatic test equipments, test economics, and quality models), Failures and Errors (definitions, failure modes, failure mechanisms, reliability defects), Faults (fault models, stuck-at faults, bridging faults, timing faults, transistor-level faults, functional-level faults, effectiveness of different fault models based on real data), Logic and Fault Simulation (fault equivalence and fault collapsing, true-value simulation, fault simulation algorithms, statistical methods), Test Generation for Combinational Circuits (algebraic methods, path-tracing (D-alg, PODEM, FAN), testability metrics, test file compression), Digital Design-For-Testability and Internal Scan Design (ad-hoc methods, scan architectures, scan-based test methodology).

For further information: http://cdnc.itec.kit.edu/

CommentTesting of digital circuits plays a critical role during the design and manufacturing cycles. It also ensure the quality of parts shipped to the customers. Test generation and design for testability are integral parts of automated design flow of all electronics products. The objective of this course is to provide the foundations for developing test methods for digital systems and provides the techniques necessary to practice design for testability.

This course encompasses the theoretical and practical aspects of digital systems testing and the design of easily testable circuits. Topics include Introduction to Testing (testing definition, types of test, automatic test equipments, test economics, and quality models), Failures and Errors (definitions, failure modes, failure mechanisms, reliability defects), Faults (fault models, stuck-at faults, bridging faults, timing faults, transistor-level faults, functional-level faults, effectiveness of different fault models based on real data), Logic and Fault Simulation (fault equivalence and fault collapsing, true-value simulation, fault simulation algorithms, statistical methods), Test Generation for Combinational Circuits (algebraic methods, path-tracing (D-alg, PODEM, FAN), testability metrics, test file compression), Digital Design-For-Testability and Internal Scan Design (ad-hoc methods, scan architectures, scan-based test methodology).

For further information: http://cdnc.itec.kit.edu/

Content of teaching

The objective of this course is to provide the foundations for developing test methods for digital systems and provides the techniques necessary to practice design for testability.

This course encompasses the theoretical and practical aspects of digital systems testing and the design of easily testable circuits. Topics include defect and fault models, test generation for combinational and sequential circuits, testing measures and costs, and design for testability.

ShortdescriptionDescription:
The objective of this course is to provide the foundations for developing test methods for digital systems and provides the techniques necessary to practice design for testability.

This course encompasses the theoretical and practical aspects of digital systems testing and the design of easily testable circuits. Topics include defect and fault models, test generation for combinational and sequential circuits, testing measures and costs, and design for testability.
Aim

The course provides the basic techniques for testing digital circuits.

Exam description

Die Erfolgskontrolle wird in der Modulbeschreibung erläutert.