To know in advance an upcoming failure or a false-behavior of a chip is important in a reliability perspective. The runtime behavior of a digital chip depends immensely on the application running on it. Hence, to predict the chip behavior in advance, it is important to capture the essence of an application and find patterns that can reflect an upcoming change in many of the runtime parameters. We aim to capture patterns in a workload phase using machine learning models that can warn against such upcoming critical scenarios. The goal of this work is to collect workload data based on simulations and predict runtime parameters based on the machine-learning model built on this data.
To give some specific details, it has been shown in the literature that a specific sequence of instructions executed on a processor can trigger on-chip effects and can lead to catastrophic scenarios. These are anomalies that could be predicted from patterns in the state-element data. We explore these effects to find observables that can predict these behavior and build models for prediction.
|Requirements:||Programming, Logic Design|
|Programming, Logic Design||FPGA, verilog, vhdl|
|Contact:||arun v∂kit edu|
Prof. Dr. Mehdi Tahoori