Edited Conference Proceedings
5. Proceedings of IEEE European Test Symposium, edited by S. Hellebrand and M. Tahoori, 2019.
4. Proceedings of IEEE International VLSI Test Symposium, edited by A. Mazumdar and M. Tahoori, 2018.
3. Proceedings of IEEE International Workshop on Defect and Current Based Testing, edited by H. Mahanaeve, M. B. Tahoori, and M. Tehranipoor, 2007.
2. Proceedings of IEEE International Workshop on Defect and Current Based Testing, edited by S. Menon, J. Plusquelic, H. Mahanaeve, and M. B. Tahoori, October 2007.
1. Proceedings of IEEE International Workshop on Defect and Current Based Testing edited by S. Menon, H. Mahanaeve, J. Plusquelic, and M. B. Tahoori, May 2005.
1. S Tan, M Tahoori, T Kim, S Wang, Z Sun, S Kiamehr, "Long-Term Reliability of Nanometer VLSI Systems Modeling, Analysis and Optimization", Springer, 2019.
Refereed Book Chapters
7. Baby, T.T., Marques, G.C., Neuper, F., Singaraju, S.A., Garlapati, S., von Seggern, F., Kruk, R., Dasgupta, S., Sykora, B., Breitung, B. and Sukkurji, P.A., 2020. Printing technologies for integration of electronic devices and sensors. In Functional Nanostructures and Sensors for CBRN Defence and Environmental Safety and Security (pp. 1-34). Springer, Dordrecht.
6. Vijayan, Arunkumar, Krishnendu Chakrabarty, and Mehdi B. Tahoori. "Machine Learning-Based Aging Analysis." Machine Learning in VLSI Computer-Aided Design. Springer, Cham, 2019. 265-289.
5. S. Kiamehr, M. Tahoori, L. Anghel, „Manufacturing Threats.” In Dependable Multicore Architectures at Nanoscale (pp. 3-35). Springer, Cham, 2018.
4. M.B. Tahoori, “Reliable Design for Crossbar Nano-architectures”, In Suzuki, Junichi, Nakano, Tadashi, Moore, Michael John “Modeling, Methodologies and Tools for Molecular and Nano-scale Communication”
3. A. Amouri, M. Tahoori, “Lifetime Reliability Sensing in Modern FPGAs”, In P. Athanas, D. Pnevmatikatos, N. Sklavos, editors, “Embedded Systems Design with FPGAs”, Springer, ISBN 978-1-4614-1361-5, 2013
2. M.B. Tahoori, “Defect Tolerance in Crossbar Array Nano-Architectures” In M. Tehranipoor, editors, “Emerging Nanotechnologies, Test, Defect Tolerance, and Reliability”, Chapter 5, Pages 121-152, Springer, ISBN 978-0-387-74746-0, 2008.
1. M.B. Tahoori, N. Jha, I. Bahar, “Testing Aspects of Nanotechnology Trends” In L.T. Wang, C.E. Stroud, N. A. Touba, editors, “System On Chip Test Architectures: Nanometer Design for Testability" Chapter 17, Pages 791-833, Elsevier, Morgan Kaufmann Publishers, ISBN 978-0-12-373973-5, 2008.
9. R. Bishnoi, F. Oboril, and M.B. Tahoori, “Magnetic Probe Based Test Methodology for Spintronic Technologies”, 2017, (EU Patent No: 17401042.1-1568).
8. R. Bishnoi, F. Oboril, and M.B. Tahoori, “Efficient Testing of a Magnetic Memory Circuit”, 2017, (EU Patent No: 17001784.2-1203).
7. R. Bishnoi, C. Münch, M.B. Tahoori, “Multi-Bit Non-Volatile Flip-Flop”, 2018, (EU Patent No: 18000262.8).
6. M.S. Golanbari, S. Kiamehr, R. Bishnoi, M. B. Tahoori,”Reliable Low-Power Memory-Based PUF Architecture”, 2018, (EU Patent No: 18000240.4).
5. F. Oboril, M. Tahoori, R. Bishnoi, “Non-Volatile Non-Shadow Flip-Flop”, EU Patent No: 16000198.8-1805 (pending)
4. H. Asadi, K. Granlund, M. B. Tahoori, D. Kaeli, “Analytical Soft Error Evaluation Tool for SRAMBased FPGAs”, Joint Patent Application by EMC Corporation and Northeastern University, January 2008.
3. A. Abdi, M. B. Tahoori, “Systems and Methods for Fault Diagnosis in Molecular Networks”, Joint Patent Application by Northeastern University and New Jersey Institute of Technology, International Patent Application Number: PCT/US08/054674, US Patent Application Number 60/902,767, February 2008 (patent pending).
2. R. Murgai, S. Reddy, T. Miyoshi, T. Horie, M. B. Tahoori, “Analyzing Substrate Noise”, US Patent Number 7246335, July 2007.
1. M. B. Tahoori, S. Toutounchi, “Method for Locating Faults in a Programmable Logic Device”, US Patent Number 6732348 B1, May 2004.
7. Christopher Münch, Master Thesis, supervised by Dr.-Ing. Rajendra Bishnoi, "Non-volatile Multibit Spin-Transfer-Torque Shadow Flipflop Design", Karlsruhe Institute of Technology (KIT), September 2017
6. Yi Fang, Master Thesis, supervised by Sarath Mohanachandran Nair and Dr.-Ing. Florian Schoen, "Characterization and Modeling of Process Variation in MEMS Development and Manufacturing", Karlsruhe Institute of Technology (KIT), July 2019.
5. Cong Dang Khoa Nguyen, Bachelor Thesis, supervised by Dennis Gnad, "Voltage-based Covert Channel Communication between logically separated IP Cores in FPGAs", Karlsruhe Institute of Technology (KIT), August 2018. [PDF]
4. Longfei Mao, Master Thesis, supervised by Nour Sayed, "STT-MRAM Performance and Energy Efficient Design based on Dynamic Behavior predictions", Karlsruhe Institute of Technology (KIT), May 2018
3. Sascha Rapp, Bachelor Thesis, supervised by Dennis Gnad, "Detecting malicious combinational cycles in FPGA bitstreams", Karlsruhe Institute of Technology (KIT), May 2018.
2. Jiao Li, Master Thesis, co-supervised by Arunkumar Vijayan, "Trace-buffer Based Electric Bug Localization", Politecnico Di Torino, April 2018.
1. Jonas Krautter, Master Thesis, supervised by Dennis Gnad, "On-Chip Fault Attack Analysis using shared FPGA resources", Karlsruhe Institute of Technology (KIT), February 2018.