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Other publications

Edited Conference Proceedings

  1. Proceedings of IEEE International Workshop on Defect and Current Based Testing, edited by H. Mahanaeve, M. B. Tahoori, and M. Tehranipour, 2007.
  2. Proceedings of IEEE International Workshop on Defect and Current Based Testing, edited by S. Menon, J. Plusquelic, H. Mahanaeve, and M. B. Tahoori, October 2007.
  3. Proceedings of IEEE International Workshop on Defect and Current Based Testing edited by S. Menon, H. Mahanaeve, J. Plusquelic, and M. B. Tahoori, May 2005.

 

Refereed Book Chapters

4.   M.B. Tahoori, “Reliable Design for Crossbar Nano-architectures”, In Suzuki, Junichi, Nakano, Tadashi,

      Moore, Michael  John “Modeling, Methodologies and Tools for Molecular and Nano-scale Communication”

3.   A. Amouri, M. Tahoori, “Lifetime Reliability Sensing in Modern FPGAs”, In P. Athanas, D. Pnevmatikatos,

      N. Sklavos, editors, “Embedded Systems Design with FPGAs”, Springer, ISBN 978-1-4614-1361-5, 2013

2.   M.B. Tahoori, “Defect Tolerance in Crossbar Array Nano-Architectures” In M. Tehranipoor,

       editors, “Emerging Nanotechnologies, Test, Defect Tolerance, and Reliability”, Chapter 5, Pages

       121-152, Springer, ISBN 978-0-387-74746-0, 2008.

1.   M.B. Tahoori, N. Jha, I. Bahar, “Testing Aspects of Nanotechnology Trends” In L.T. Wang, C.E.

       Stroud, N. A. Touba, editors, “System On Chip Test Architectures: Nanometer Design for Testability"

 

      Chapter 17, Pages 791-833, Elsevier, Morgan Kaufmann Publishers, ISBN 978-0-12-373973-5, 2008.

 

 

PATENTS

 

5.       F. Oboril, M. Tahoori, R. Bishnoi, “Non-Volatile Non-Shadow Flip-Flop”,  EU Patent No: 16000198.8-1805 (pending)

4.       H. Asadi, K. Granlund, M. B. Tahoori, D. Kaeli, “Analytical Soft Error Evaluation Tool for SRAMBased

          FPGAs”, Joint Patent Application by EMC Corporation and Northeastern University, January 2008.

3.       A. Abdi, M. B. Tahoori, “Systems and Methods for Fault Diagnosis in Molecular Networks”, Joint

          Patent Application by Northeastern University and New Jersey Institute of Technology, International

          Patent Application Number: PCT/US08/054674, US Patent Application Number 60/902,767,

          February 2008 (patent pending).

2.       R. Murgai, S. Reddy, T. Miyoshi, T. Horie, M. B. Tahoori, “Analyzing Substrate Noise”, US Patent

          Number 7246335, July 2007.

1.       M. B. Tahoori, S. Toutounchi, “Method for Locating Faults in a Programmable Logic Device”, US

          Patent Number 6732348 B1, May 2004.