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On the deployment of on-chip noise sensors in 3D ICs

On the deployment of on-chip noise sensors in 3D ICs
chair:

Chair of Dependable Nano Computing (CDNC)

links:
Kontaktperson:

M.Sc. Eng. Shengcheng Wang


Description:

The continuous increase in power density brought by the CMOS scaling has resulted in a monotonic decrease to the supply voltage. On the other hand, to avoid excessive leakage power, the threshold voltage cannot be scaled at the same pace. At a result, the reduced power noise margin, along with the boost in functional complexity, has posed severe threat to the power integrity of the chips. In this condition, noise margin violation will lead to undesired effects such as delay degradation and timing violation, eventually causing system malfunctioning. Therefore, the run-time detection of noise margin violation is necessary for guaranteeing the power integrity of the chips.

In this work, we study the run-time noise management for three-dimensional integrated circuits (3D ICs), which offer one of the most practical solution to extend Moore's Law. The objective of this work is to consider the co-optimization of the placement of power/ground (P/G) through-silicon vias (TSVs) and power noise sensors.

Requirements:

Programming skills of C++

Preferred knowledge:

Knowledge about statistics and matrix theory


Contact:
   M. Sc. Shengcheng Wang (Email: shengcheng.wang@kit.edu)
Please prepare your curriculum vitae and list of the learned courses before.