As CMOS VLSI technologies enter the nanometer scales, embedded systems become more vulnerable to various aging effects, such as transistor aging due to negative and positive bias temperature instability and hot electron injection, as well as dielectric breakdown and electromigration. These can significantly increase the delay of devices causing more timing failures in the field and eventually faster wearout of the system. Current approaches for addressing wearout issues are largely scattered, mostly focusing at the device/circuit level, and relatively few approaches at higher levels of design.
In this project we will develop a set of comprehensive techniques to address accurate and technology-relevant modeling of various aging effects in different levels of abstraction, from device to software layer. With the help of this modeling infrastructure, which is combined with existing performance and power modeling toolset, we propose efficient mitigation of aging effects across various levels of abstraction, from circuit to software. We combine (static) design time approaches together with (dynamic) runtime adaptation techniques to balance lifetime, performance, and power. We believe that this holistic approach enables us to maximize the lifetime operation of embedded systems with minimal cost, performance, and power impacts.