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Testing Digital Systems II

Testing Digital Systems II
type: Vorlesung (V)
semester: SS 2012
time: 17.04.2012
11:30-13:00
50.34 Raum -101


24.04.2012
11:30-13:00
50.34 Raum -101

08.05.2012
11:30-13:00
50.34 Raum -101

15.05.2012
11:30-13:00
50.34 Raum -101

22.05.2012
11:30-13:00
50.34 Raum -101

29.05.2012
11:30-13:00
50.34 Raum -101

05.06.2012
11:30-13:00
50.34 Raum -101

12.06.2012
11:30-13:00
50.34 Raum -101

19.06.2012
11:30-13:00
50.34 Raum -101

26.06.2012
11:30-13:00
50.34 Raum -101

03.07.2012
11:30-13:00
50.34 Raum -101

10.07.2012
11:30-13:00
50.34 Raum -101

17.07.2012
11:30-13:00
50.34 Raum -101

lecturer: Prof. Dr. Mehdi Baradaran Tahoori
sws: 2
lv-no.: 24637

 

Objective:

The objective of this course is to provide the foundations for developing test methods for digital systems and provides the techniques necessary to practice design for testability.

This course encompasses the theoretical and practical aspects of digital systems testing and the design of easily testable circuits. Topics include defect and fault models, test generation for combinational and sequential circuits, testing measures and costs, and design for testability.

Description:

Testing of digital circuits plays a critical role during the design and manufacturing cycles. It also ensures the quality of parts shipped to the customers. Test generation and design for testability are integral parts of automated design flow of all electronic products. The objective of this course is to provide more advanced topics on testing of digital systems and complement the foundation covered in Testing Digital Systems I. Topics include Functional and Structural Testing (design verification vectors, exhaustive test, pseudo-exhaustive test, pseudo-random testing), Essentials of Test Generation for Sequential Circuits (state-machine initialization, time-frame expansion method), Built-in Self-Test (test economics of BIST, test pattern generation, output response analysis, BIST architectures), Boundary Scan (Boundary scan architectures, BS test methodology), Delay Testing (path delay test, hazard-free, robust, and non-robust delay tests), transition faults, delay test schemes), Current-Based Testing (motivation, test vectors for IDDQ, variations of IDDQ), Memory Test (memory test algorithm, memory BIST, memory repair), and DFT for System-on-Chip.